The present disclosure relates generally to electronic circuits, and more particularly, to phase locked loop circuits. Still more particularly, the present disclosure relates to methods for detecting locks in a phase locked loop.
Phase locked loops (PLLs) are widely used in electronic designs such as radios, television receivers, video apparatuses, satellite broadcasts and instrumentation systems. PLLs are electronic circuits with a voltage or current-driven oscillator that is constantly driven to match the frequency of an input signal. Typically, a PLL circuit includes a voltage control oscillator (VCO) that first tunes a circuit frequency close to the desired frequency. A lock detection circuit then sends information signals to VCO such that VCO can re-adjust and lock in the frequency. If VCO overcompensates, the lock detection circuit re-adjusts the signal sent to VCO. In other words, VCO and the lock detection circuit work together through feedbacks to and from each other.
Among the purposes of a lock detection circuit in electronic designs are: to evaluate the quality of the output information, and to deliver out-of-lock rate information to the underlying electronic circuit such that bandwidth of the PLL can be readjusted appropriately. Lock detection is based on a number of variables, including but not limited to: time derivative, or the out-of-phase radians per unit time, the variance of the phase error, and cycle slips.
Depending on application areas and desired phase locking characteristics, phase locked loop detection may be implemented in a variety of circuits, including analog-only circuits, or mixed signal (analog/digital) circuits. Typically, lock detection is based on time derivative, measurable by the time delay between a rising edge of an input signal, and a rising edge of a carrier signal, and relative to the cycle time of the latter. Such a lock detection setup typically includes a phase-and-frequency detector (PFD), which delivers lock detection information such as the time delay between the rising edges of an input signal and a carrier signal.
PFD also delivers information with respect to momentary phase error in the form of pulse widths. A subsequent analysis of the said pulse widths and their corresponding pulse energies may yield information as to whether the one signal is locked against the other. Momentary pulse energy levels may also be averaged over time to yield a smoother value that can be compared against a threshold value by presetting the threshold value in a voltage comparator such as a Schmitt trigger and comparing the average value against the threshold value.
PFD also delivers information critical to understanding cycle slip, which is phase shift equal to one or a multiple of a carrier frequency's period. Cycle slip happens when a weak or noisy signal causes a change in the signal tracking point of the carrier frequency, thereby temporarily losing lock.
Desirable in the art of semiconductor memory design are improved designs and methods with which better control of lock detection in PLL circuits can be achieved.